1. Field of the Invention
The invention relates to a circuit apparatus and a method of manufacturing the same.
2. Description of the Related Art
Portable electronics equipment including cellular phones, PDAs, DVCs, and DSCs has been advancing at increasingly fast speed. Under the circumstances, miniaturization and weight saving have become essential in order for these products to be accepted in the market. To achieve this, system LSIs of higher integration have been sought after. Meanwhile, enhanced usability and convenience have been desired of such electronics equipment, and functional and performance sophistication has been required of the LSIs to be used for the equipment. Consequently, while the LSI chips of higher integration have grown in the number of I/Os, miniaturization has been highly required of the packages themselves. For the sake of satisfying both the requirements, there has been a strong demand to develop a semiconductor package suited to packaging semiconductor parts on a board at a higher density. To meet this demand, various types of packaging technologies called CSP (Chip Size Package) have been developed.
Among the known examples of such packages is a BGA (Ball Grid Array). In the BGA, semiconductor chips are mounted on the packaging board and molded with a resin before solder balls are formed over an area on the other side of the board as external terminals. Since the BGA realizes a planar mounting area, the package can be miniaturized relatively easily. Besides, the circuit board need not be rendered in narrower pitches, which eliminates the need for high-precision mounting technologies. The BGA can thus be used to reduce the total packaging cost even when the package itself costs relatively high.
FIG. 8 is a diagram showing the general configuration of a typical BGA. The BGA 100 has the structure that an LSI chip 102 is mounted on a glass epoxy board 106 via an adhesive layer 108. The LSI chip 102 is molded with a sealing resin 110. The LSI chip 102 and the glass epoxy board 106 are electrically connected with metal wires 104. Solder balls 112 are arranged in an array on the backside of the glass epoxy board 106. Through these solder balls 112, the BGA 100 is mounted on a printed wiring board.
In such a package, semiconductor chips are sealed by using such techniques as transfer molding, injection molding, potting, and dipping (for example, see Japanese Patent Laid-Open Publication No. Hei 8-162486).
Techniques for achieving a low-profile system LSI of even higher precision and performance have also been disclosed. In the techniques, thin-film technologies and thick-film technologies are used to cover a base board unit with a layer that contains passive elements composed of resistor parts, capacitor parts, and/or pattern wiring parts which are supplied with power or signals from the base-board side through a dielectric insulating layer (for example, see Japanese Patent Laid-Open Publication No. 2002-94247).
Moreover, as an approach to an improved heat radiation characteristic of the system LSI, technologies for using a metal or semiconductor board have also been disclosed (for example, see Japanese Patent Laid-Open Publication No. Hei 10-223832).
According to those conventional CSPs as disclosed in Japanese Patent Laid-Open Publication No. Hei 8-162486, however, it has been difficult to achieve portable electronic equipment and the like that are reduced in size, profile, and weight up to the levels desired at present. The improvement to the heat radiation characteristic has also been limited.
In the techniques of forming a layer containing passive elements composed of resistor parts, capacitor parts, and/or patterned wiring parts as disclosed in Japanese Patent Laid-Open Publication No. 2002-94247, highly complicated processes are used for forming the thin films or thick films. In terms of the manufacturing cost of the passive elements, there has thus been room for further improvement. These complicated processes also have difficulty in flattening the surfaces of the passive elements. There has thus been room for further improvement even in terms of manufacturing stability.
When a metal or semiconductor board is used as disclosed in Japanese Patent Laid-Open Publication No. Hei 10-223832, the adhesiveness between the board and insulating films may be insufficient, possibly causing exfoliation and contributing to a drop in yield. Furthermore, when electronic parts such as an IC chip are mounted on the board, the electronic parts may fall outside their predetermined positions due to insufficient position accuracy. This can also contribute to a drop in yield.